Integrated circuit shapes can be patterned on a wafer entirely by means of direct writing electron beam (e-beam) lithography. Using e-beam to write microcircuit patterns in integrated circuit fabrication is well known in the art. The intended pattern can be directly written onto the wafer by exposing a thin layer of radiation sensitive material on the wafer with a beam of electrons or, alternatively, by using a mask made with an e-beam tool to optically expose a thin layer of photoresist on the semiconductor wafer. Whether the pattern is directly written or indirectly written with a mask, the e-beam tool control remains the same. See generally, U.S. Pat. 4,789,945 for an example of direct writing e-beam lithography used to expose to an entire wafer. The use of a computer to control the e-beam is also well known. See U.S. Pat. No. 4,728 797 for an example of a computer controlled microcircuit. fabrication system.
While e-beam lithography provides the advantage of very sharply defined patterns for very small geometric shapes, transferring those shapes from a computer designed shape to a physical image on a photoresistive, or radiation sensitive layer (resist), can be both expensive and time consuming. Most of the cost associated with transferring the shape is computer operating cost, which is also generally time dependent. Therefore, reducing computer operating time will reduce both the time and the expense associated with e-beam lithography. Several approaches have been used to reduce the time required to expose a wafer with an e-beam tool. See U.S. Pat. No. 4,147,937 for an example of a method and an apparatus for exposing a wafer by raster scan writing, i.e., a single line at a time. See also, U.S. Pat. No. 4,914,304 for an example of an e-beam exposure system that uses a shaped beam to improve exposure of different shapes. Although these prior art approaches reduce the exposure time, they do not appreciably reduce the computer time required to convert the design shape into Numerical Control for the e-beam tool (process a design shape). Using the prior art method of processing design shapes, it sometimes takes several hundreds of Central Processing Unit (CPU) minutes to convert an entire design into a format which may be used to control an e-beam tool. So, converting the graphics representation of a shape to control parameters for controlling the e-beam tool is a major computer bottleneck.
THe flow diagram of FIG. 1 shows the steps typically taken in the prior art to convert design data into e-beam tool control data and expose a semiconductor wafer. Each design shape is represented (30) in a graphics language by lines, rectangles, circles, and polygons. Such a representation is characteristic of the particular graphics language used and the shape represented. The graphics representation of the shape must be converted to control signals for an e-beam tool. The e-beam tool uses the converted, or postprocessed, information to direct the electron beam onto the radiatio.n sensitive layer, which writes, or exposes, the design shape onto the layer. A postprocessor is a computer program which combines the graphics data (30) and key e-beam tool processing parameters (32), also called keywords, to produce Numerical Control (NC) data for use by the e-beam lithographic exposure tool. Converting the design data to numerical control data iis called postporcessing the design data. Numerical control data is the data used to control exposure of the radiation sensitive layer by the e-beam tool.
Before postprocessing the design data, the graphics language representation of the design data (30) and the keywords (32) are checked (34) for syntax errors. After verifying that there are no syntax errors, the postprocessor decomposes (36) each design shape into a series of edges and then labels (38) each edge. An edge is a portion of the shape's perimeter and is normally a straight line connecting two vertices on the shape. Each converted edge is labeled (38) according to its position on a shape as a top, bottom, right or left edge. The postprocessor then applies (40) keywords which describe shape compensation, known as etch biases, to the edges. An etch bias is a compensation for the amount of distortion to a design shape which occurs in the process of making the final shape. The postprocessor then transforms (42) the edges from the graphics language grid (a unit of measure) to the e-beam tool grid. Alternatively, the postprocessor may apply the etch biases (40) to the shapes and transform the shapes (42) from the graphics grid to the tool grid before converting the shapes to edges (36) and labeling the edges (38).
After transforming the shapes into the tool grid, the postprocessor fills (44) the shapes. "Filling" is a term used to describe the process of reconstructing a shape out of one or more types of polygons, such as rectangles, so that the reconstructed shape is, as nearly as possible, identical to the design shape. The design shape is said to be filled with fill polygons or fill rectangles. See U.S. Patent No. 4,554,625 for an example of a method of producing non-overlapping rectangles to fill a shape. During the fill, some undesirably small rectangles, called slivers, may have been created. A sliver is a rectangle whose height or width is less than a sliver size, a size defined in the keywords (32). Slivers are usually narrower than the narrowest rectangle the e-beam tool can correctly expose. The presence of a sliver rectangle in the fill rectangles for a shape will cause distortion in the microcircuit. In some extreme cases, the presence of slivers can lead to reduced integrated circuit chip production (known as yield loss) or lead to defective integrated circuit chips that fail much sooner than would the identical chip without the presence of slivers If the same shape could be filled without creating slivers then the fill is not optimum. The fill also may not be optimum because the shape could have been filled with fewer rectangles. So, prior art methods required that each shape be filled twice: once to fill the shape and a second time to determine if the first fill was optimum. The second fill may take as much CPU time and generate as much data volume as or more than the first fill.
The fill rectangles provide the e-beam tool with control data to direct the e-beam to expose a rectangular area. See, "Method and Apparatus for Digital Control of E-Beam Pattern Writing as Applied to Subfield and Vector Equipment," in the March, 1980 IBM Technical Disclosure Bulletin page 4583 and see, "Method and Apparatus to Provide Rapid Interpretation of Digital Source Information During Electron-Beam Pattern Writing of Rectangular Shapes," in the April, 1982 IBM Technical Disclosure Bulletin page 5681 for examples of rectangle generators. U.S. Patent No. 3,956,634 discloses a method of exposing a fill rectangle by an inward spiral, which starts by tracing the perimeter of the rectangle and spiralling the beam inward until the center of the rectangle is reached.
After the fill (44), overlapping fill rectangles were cut and the overlaps were eliminated (46). Overlaps occurred when a designer used two or more overlapping simple shapes to create a more complex shape As a result of filling each of the simple shapes, the more complex shape was filled However, the fill rectangles overlapped whenever the simple shapes overlapped The overlap can be eliminated by either combining the overlapping fill rectangles into a single fill rectangle, by shrinking one of the overlapping fill rectangles, by removing the overlapping fill rectangles and filling along the overlap, or, by any other method which would result in butting fill rectangles filling the area within the complex shape. The fill rectangle overlaps may be eliminated (46) in the second pass of the fill (44) or after the second pass of the fill (44). Once the fill rectangle overlaps are eliminated (46) the fill rectangles are proximity corected (47).
Proximity correction (47) means adding control information to the fill rectangles to adjust the length of time the e-beam must expose the resist in order to print a clear image. After proximity correction, the fill data is passed (48) to the e-beam tool as Numerical Control (NC) data. NC data is actually a series of commands for the e-beam tool to control the tool to expose each rectangle. The e-beam tool writes (50) the design onto a wafer by exposing each fill rectangle onto the resist. After every fill rectangle has been written, the design shape will have been written onto the resist layer. The exposed pattern can be developed in a manner similar to to photodeveloping. The wafer, covered by the developed pattern, is then etched, implanted or otherwise similarly altered to imprint the pattern onto the wafer. So, the Numerical Control data for the e-beam tool is generated from the data generated during the fill and proximity correction. Since the computer must treat every shape as a puzzle in which the computer must both create the pieces and then fit them together during the fill (44) and, since the computer must then calculate the effect on a fill rectangle from every fill rectangle in close proximity during proximity correction (47), the fill (44) and proximity correction (47) use the most CPU time and produce the largest volume of data.
A semiconductor chip, typically, is comprised of several layers of shapes commonly known as levels and which are overlaid to form micro circuits. In the prior art, when each of these layers was created optically through a mask, these layers were known as mask levels. Some levels may still be made optically on the wafer, while the masks are made with an e-beam tool. A single design may require several levels which must be independently converted to E-beam control data. Filling each mask level is a major CPU bottleneck which may take several CPU hours with prior art fill methods. The CPU thruput times tend to increase with N**2, where N is the number of shape edges. Since each circuit is comprised of several design shapes, and since the number of edges is directly related to the number of design shapes, CPU thruput is related to the number of circuits in the design If a design is sufficiently complex, the time required to fill a single mask level would exceed the average time between CPU failures, known as the CPU's mean time to fail. Thus, the number of circuits allowed on an integrated circuit chip could be limited by factors such as the CPU's mean time to fail rather than the e-beam tool's other physical limitations when a prior art fill is used. Reducing the time required to fill a design would provide a significant improvement over slow prior art fill methods.
Also, besides being slow and awkward, prior art fill methods may lead to a unfavorable cutting of slanted edges Filling along a slanted edge may be done by placing a staircase of small rectangles along the edge. Fragmenting the edge unequally may result in edge variations from staircases of varying size being placed along each piece of the angled edge. So, the uniformity of that angled edge is often lost, degrading image quality.